1. Field of the Invention
The present invention relates to a booster circuit and a PWM signal generator, and more particularly, to a booster circuit and a PWM signal generator that control a control state of a driving transistor in accordance with magnitude of load current that flows in a load circuit connected to a booster circuit.
2. Description of Related Art
Booster circuits are able to generate voltage that is higher than an input voltage (for example, voltage of main power supply). One of the booster circuits includes a booster circuit of coil boosting type. The booster circuit of coil boosting type includes a driving transistor where conduction state is controlled by a PWM signal, and a voltage-boosting coil that is connected between a main power supply and the driving transistor. The booster circuit drives the voltage-boosting coil by the driving transistor to generate the boosted voltage.
In recent years, a duty ratio of the PWM signal that drives the driving transistor is controlled in accordance with the magnitude of load current consumed in a load circuit connected to a booster circuit in order to decrease power consumption of the booster circuit. For example, when the load current is large, the duty ratio of the PWM signal is increased to make the time that the driving transistor is conducted longer to sufficiently provide large load current. On the other hand, when the load current is small, the duty ratio of the PWM signal is decreased to make the time that the driving transistor is conducted shorter to reduce power consumption.
However, in a control terminal (gate terminal, for example) of the driving transistor, an input parasitic capacity is formed. Thus, when the PWM signal is supplied to the driving transistor, current to charge the input parasitic capacity to the voltage value in accordance with the amplitude is required regardless of the duty ratio of the PWM signal. Typically, the input parasitic capacity of the driving transistor used in the booster circuit has a large capacitance, which requires larger volume of current for charging. Thus, there is a problem that the power consumption cannot sufficiently be reduced in the booster circuit due to the charge current to the input parasitic capacity even when the duty ratio is decreased. To deal with this problem, a technique of reducing power consumption when the load current is small is disclosed in Japanese Unexamined Patent Application Publication No. 2004-96967.
FIG. 5 shows a circuit diagram of a booster circuit 100 disclosed in Japanese Unexamined Patent Application Publication No. 2004-96967. As shown in FIG. 5, in the booster circuit 100, an internal power supply circuit 115 varies the voltage value of an internal power supply Vcc according to the current that flows in a driving transistor 103. Then, a driver 113 drives the driving transistor 103 by a PWM signal having amplitude in accordance with the voltage value of an internal power supply Vcc. As such, the booster circuit 100 is able to drive the driving transistor 103 by the PWM signal having small amplitude when the load current is small. In other words, the booster circuit 100 is able to reduce charging and discharging current of the driving transistor 103 to an input parasitic capacity Ciss when the load current is small, so as to reduce the power consumption when the load is small.